The present invention relates to testing non-core memory management units (MMUs).
Typically, processing cores include at least one MMU (referred to herein as core MMUs) for performing virtual to physical address translations. For example, the processing core may assign blocks of virtual memory to different processes executing on the processor (e.g., operating systems or user applications). Each of the virtual addresses corresponds to a physical memory address in memory. The mappings between the virtual and physical addresses are stored in a page table as page table entries. The page table is typically stored in main memory.
When a process sends a request to a processing core to read data from, or write data to, a particular virtual address, the MMU queries the page table (or a translation lookaside buffer) to identify the corresponding physical address. The processing core then uses the physical address to perform the read or write requested by the process.